DocumentCode
2727553
Title
P-MOSFET gate current and device degradation
Author
Ong, Tong-Chern ; Seki, Koichi ; Ko, Ping K. ; Hu, Chenming
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
1989
fDate
17-19 May 1989
Firstpage
193
Lastpage
196
Abstract
Hot-carrier-limited device lifetime of surface-channel p-MOSFETs (p-channel metal-oxide-semiconductor field-effect transistors) is found to correlate well with gate current over a wide range of bias. The same result is not observed for buried-channel p-MOSFETs. A gate current model for surface-channel p-MOSFETs is presented. Using this gate current model, reasonable estimates of AC (pulse) stress lifetime can be made based on DC stress data
Keywords
carrier lifetime; hot carriers; insulated gate field effect transistors; semiconductor device models; AC stress lifetime; bias; device degradation; gate current; gate current model; hot-carrier-limited device lifetime; surface-channel p-MOSFETs; CMOS technology; Degradation; Electron traps; Hot carriers; Implants; Life estimation; Lifetime estimation; MOSFET circuits; Monitoring; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location
Taipei
Type
conf
DOI
10.1109/VTSA.1989.68612
Filename
68612
Link To Document