• DocumentCode
    2727586
  • Title

    Improving a 3 Data-Source Diagnostic Method

  • Author

    Hariri, Y. ; Thibeault, C.

  • Author_Institution
    Dept. of Electr. Eng., Ecole de Technologie Superieure, Montreal, Que.
  • fYear
    2006
  • fDate
    38869
  • Firstpage
    149
  • Lastpage
    152
  • Abstract
    In this paper, we present improvements to a diagnosis method for bridging faults combining three different data sources. The first data source is a set of IDDQ measurements used to identify the most probable fault type. The second source is a list of parasitic capacitances extracted from layout and used to create a list of realistic potential bridging fault sites. The third source is logical faults detectable at the primary outputs (including scan flip flops), used to limit the number of suspected gates. Combining these data significantly reduces the number of potential fault sites to consider in the diagnosis process. The modifications proposed in this paper allow the technique to be even more suitable for very large devices. Results obtained with different circuits are provided
  • Keywords
    circuit testing; fault simulation; current measurements; data source diagnostic; fault type identification; logical faults; parasitic capacitance; Bridge circuits; CMOS logic circuits; CMOS technology; Circuit faults; Failure analysis; Fault detection; Fault diagnosis; Histograms; Parasitic capacitance; Software testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006 IEEE North-East Workshop on
  • Conference_Location
    Gatineau, Que.
  • Print_ISBN
    1-4244-0416-9
  • Electronic_ISBN
    1-4244-0417-7
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2006.250899
  • Filename
    4016930