On the Design of a Double Precision Logarithmic Number System Arithmetic Unit

This paper investigates the integration of a 64-bit LNS arithmetic unit into a conventional microprocessor. The goals are to devise an LNS unit that can be faster than an FPU for a broad range of applications, and to minimize the added hardware. Two ways of implementing the logarithmic sum and difference functions are studied. One way uses higher-order Taylor series implemented by look-up tables and interpolation, while the other is based on a CORDIC engine. It is shown that a look-up table based implementation is fairly competitive to a floating-point unit in terms of clock rate, overall latency and repeat rate, at the expense of some cache pressure, while the CORDIC-based implementation is fast, has a repeat rate of one clock cycle, and supports complex operations but at the cost of a higher gate count