Split H-tree Design Method for High-Performance GALS Systems

Clocking an entire chip through a conventional H-tree clock distribution network, in deep sub-micron technologies, is becoming increasingly difficult. Various timing constraints, including skew budget due to process variations, put a limit on the fastest speed a chip can work at. In this paper, a design methodology is proposed to relax the timing constraints by a substantial factor, up to 6 times. This performance is achieved by splitting the H-tree into smaller modules and making the different modules communicate via mesochronous or asynchronous interfaces, this type of system is commonly known as globally asynchronous locally synchronous (GALS). A closed-form mathematical model for the length of interconnects, after successive splittings, is formulated. Simulation results support our analytical findings that split H-trees allow clocking chips, of a particular die size, at a higher frequency. Moreover, a comparison of different asynchronous communication mechanisms is achieved to suggest an optimum design based on the target system performance