A bandpass mismatch-shaped multi-bit /spl Sigma//spl Delta/ switched-capacitor DAC using butterfly shuffler

In the context of a /spl Sigma//spl Delta/ analog-to-digital converter (ADC) or digital-to-analog-converter (DAC), single-bit quantization is preferred because a 1b DAC is inherently linear. A multi-bit DAC needs to be linear to avoid being the performance-limiting factor in a CB converter. Aside from this drawback, multi-bit quantization is attractive because it improves /spl Sigma//spl Delta/ modulator performance by increasing the modulator resolution or increasing the modulator bandwidth, while at the same time whitening the quantization noise and improving modulator stability. Among many dynamic-matching schemes existing today, the butterfly shuffler is effective and practical. Thus far, schemes based on the butterfly shuffler are used to whiten or to 1/sup st/-order shape mismatch errors. This paper presents a model of the structure which shows how a butterfly shuffler can be endowed with "arbitrary" mismatch-shaping characteristics. A 2/sup nd/-order bandpass shuffler is given as an example. A 16-element switched-capacitor (SC) DAC is designed and fabricated with a 1.2 /spl mu/m double-poly CMOS process. An 8/sup th/-order bandpass /spl Sigma//spl Delta/ modulator is implemented on a Xilinx FPGA along with the 2/sup nd/-order bandpass shuffler to drive the DAC. The system diagram is shown. The harmonic distortion is reduced by as much as 27 dB, resulting in a dynamic range of 90 dB at 125 kHz center frequency.