Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors

This paper describes the modeling and optimization of a hierarchical ring interconnect for system-on-chip multiprocessors. We have selected hierarchical rings for study because they exhibit properties which lend themselves to efficient SoC interconnects. Using our model, we are able to tune certain design parameters in order to reduce energy consumption. We also use dynamic clock throttling which efficiently reduces the energy consumption of the interconnect without adversely affecting system performance