Title :
A 500 MHz 64b RISC CPU with 1.5 MB on-chip cache
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
A 64b quad issue PA-RISC microprocessor with full out-of-order execution is migrated from 0.5 /spl mu/m CMOS into an advanced 0.25 /spl mu/m CMOS process. Features include an integrated on-chip 1.0 MB L1 data and 0.5 MB L1 instruction caches and a dual-voltage memory bus interface. The processor incorporates 116 M transistors on a 21.3/spl times/22 mm/sup 2/ die running in excess of 50O MHz at 85/spl deg/C and 2.0 V and delivering greater than 32 SPECint95 and greater than 52 SPECfp95 in a 440 MHz product configuration.
Keywords :
cache storage; integrated circuit design; microprocessor chips; reduced instruction set computing; 0.25 micron; 1.5 Mbit; 500 MHz; 64 bit; 85 degC; data cache; dual-voltage memory bus interface; instruction cache; on-chip cache; out-of-order execution; product configuration; quad issue PA-RISC microprocessor; Central Processing Unit; FETs; Feedback circuits; Frequency; Impedance; Reduced instruction set computing; Solid state circuits; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759129
