Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and thermo-electrical device simulations we are able to use device-internal quantities such as the electric field or the temperature distribution to find the optimal transistor layout. Guided by simulation we are able to guarantee that the avalanche breakdown propagates properly along a single meander-like collector junction. Experimental result from measurements show that this is crucial for better ESD performance of a space efficient device. Our optimized device reaches 83% of the second breakdown trigger current of a straight device. Compared to a unoptimized meander-like device we could increase its performance by 63%. The good agreement between measurements and simulation for different shapes of transistors validates our methodology and approach to optimization of ESD devices.