Title :
609 MHz G5 S/399 microprocessor
Author :
Northrop, G. ; Averill, R. ; Barkley, K. ; Carey, Sean ; Chan, Yan-Cheong ; Chan, Y.H. ; Check, M. ; Hoffman, D. ; Huott, W. ; Krumm, B. ; Krygowski, C. ; Liptay, J. ; Mayo, M. ; McNamara, T. ; McPherson, Tristram ; Schwarz, Egbert ; Siegel, L.S.T. ; Webb
Author_Institution :
IBM Corp., Poughkeepsie, NY
Abstract :
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and an IEEE compliant binary floating-point. The microprocessor operates at 600 MHz at the fast end of the process distribution, although the system is shipped at 500 MHz in a 10+2 SMP configuration. Measured system performance on the 10 way is 1069 S/390 MIPs. This microprocessor uses a 0.25 mum CMOS process. The chip uses 6 levels of metal plus an additional layer of local interconnect and is 14.6times14.7 mm2 with 25 M transistors (7 M logic/18 M array). Power supply is 1.9 V. Chip power is 25 W at 500 MHz
Keywords :
CMOS digital integrated circuits; buffer circuits; floating point arithmetic; integrated circuit interconnections; microprocessor chips; 0.25 micron; 1.9 V; 25 W; 500 MHz; 600 MHz; CMOS process; IBM G5 S/399 microprocessor; IEEE compliant binary floating-point; chip power supply; fifth-generation CMOS server; instruction branch target buffer; local interconnect; process distribution; Circuit noise; Clocks; Drives; Microprocessors; Phase locked loops; Semiconductor device measurement; Solid state circuits; Timing; Wires; Working environment noise;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759131
