Title :
A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage applications
Author :
Nozoe, A. ; Kotani, Hiroaki ; Tsujikawa, Tomonobu ; Yoshida, Kenta ; Furusawa, Kazuya ; Kato, Masaaki ; Nishimoto, Takuya ; Kume, Hideyuki ; Kurata, H. ; Miyamoio, N. ; Kubono, S. ; Kanamitsu, I. ; Koda, Kensuke ; Nakayama, Taiki ; Kouro, Y. ; Hosogane, A
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.
Keywords :
CMOS memory circuits; VLSI; cellular arrays; flash memories; multivalued logic; 0.26 micron; 2 MB/s; 256 Mbit; AND-type memory cell; CMOS; logical sector size; mass storage applications; multilevel flash memory; program rate; program throughput; program times; sector erase; Flash memory; Latches; Paper technology; Reactive power; Solid state circuits; Temperature dependence; Temperature sensors;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759156
