DocumentCode
2728349
Title
If It´s All about Yield, Why Talk about Testing?
Author
Segers, René
Author_Institution
NXP Semicond., Eindhoven
fYear
2007
fDate
20-24 May 2007
Firstpage
3
Lastpage
3
Abstract
This talk will discuss the evolution of test and diagnosis, in the broad sense, over the recent years as well as the outlook into the future. Test, as it was only recently a pure discriminator between good and bad, has gained significant more added value by acting also a feedback loop towards the manufacturing process of integrated circuits. Of course, this feedback loop was already there, but was limited to information on test bin level from a tester. In the last couple of years, this has changed dramatically, and we are now able to pinpoint to circuit coordinates and/or to circuit structures as potential candidates for low yield causes. By linking this diagnosis information to in-line data, a more than direct link to a root cause in the fab can be achieved. And this is not the end of the story. By linking diagnosis to the layout one should be able to even stronger and quicker close the loop between Design, Manufacturing and Test. All of the above will be discussed in the talk, which in a sense could mean that the talk is all about DfX, Design for excellence ...
Keywords
design for testability; integrated circuit layout; integrated circuit testing; integrated circuit yield; design for manufacturing; design for test; diagnosis information; discriminator; feedback loop; integrated circuit layout; integrated circuit manufacturing process; integrated circuit testing; integrated circuit yield; Circuit testing; Consumer electronics; Coupling circuits; Engineering profession; Feedback loop; Integrated circuit testing; Joining processes; Manufacturing processes; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2007. ETS '07. 12th IEEE European
Conference_Location
Freiburg
Print_ISBN
0-7695-2827-9
Type
conf
DOI
10.1109/ETS.2007.27
Filename
4221565
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