Title :
Improving Digital IC Testing with Analog Circuits
Author_Institution :
Dept. of Electr. Eng., Ecole de Technologie Superieure, Montreal, Que.
Abstract :
This paper presents a promising new scan-based test technique compatible with low cost testers, called captureless delay testing (CDT). This technique uses a modified scan-chain structure, improved with analog circuits. CDT is a top-off technique multiplying the number of delay test patterns, without increasing the pattern count stored in the tester memory. It comes at a minimum performance and area overhead, with a good potential for automation
Keywords :
analogue circuits; analogue storage; automatic test pattern generation; boundary scan testing; integrated circuit testing; analog circuits; captureless delay testing; delay test patterns; digital IC testing; modified scan-chain structure; scan-based test technique; tester memory; Analog circuits; Analog integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Clocks; Delay; Digital integrated circuits; Integrated circuit testing; System testing;
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
DOI :
10.1109/NEWCAS.2006.250948
