DocumentCode
2728511
Title
A 14 b 100 Msample/s CMOS DAC designed for spectral performance
Author
Bugeja, A.R. ; Bang-Sup Song ; Rakers, P.L. ; Gillig, S.F.
Author_Institution
Illinois Univ., Urbana, IL, USA
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
148
Lastpage
149
Abstract
At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.
Keywords
CMOS integrated circuits; constant current sources; digital-analogue conversion; integrated circuit design; 0.8 micron; 14 bit; 750 mW; CMOS; DAC; SFDR; clock frequencies; dynamic performance; gate length; output stage circuit; resolution; signal frequencies; spectral performance; speed; CMOS process; Capacitors; Clocks; Decoding; Frequency; Linearity; Optical wavelength conversion; Switches; Switching circuits; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759168
Filename
759168
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