Design and Implementation of High Sampling Rate Programmable FIR Filters in FPGAs

This paper investigates the design and implementation of programmable FIR filters in FPGAs, for applications requiring the highest sampling rates. A comparison of architectures is made, with a quantitative evaluation of the direct and direct transposed forms in terms of logic resources. A qualitative assessment of placement and routing issues is also made. Two types of programmable filters are considered. In the first case, all coefficients are allowed the same dynamic range. In the second case, programmability is allowed but for a restricted set of linear phase filters where the center coefficients are allotted more bits. Implementation details leading to a cost and performance comparison are given. For a filter with 32 coefficients, the transposed form requires 11% and 32% more arithmetic resources for the general and restricted cases, respectively, and 24% fewer memory elements in either case