PPM Reduction on Embedded Memories in System on Chip

Author

Hamdioui, Said ; AL-Ars, Zaid ; Jimenez, Javier ; Calero, Jose

Author_Institution

Comput. Eng. Lab., Delft Univ. of Technol., Delft

fYear

2007

fDate

20-24 May 2007

Firstpage

85

Lastpage

90

Abstract

This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of Systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality.

Keywords

integrated circuit reliability; integrated circuit testing; system-on-chip; PPM reduction; deep-submicron memory technology; dynamic faults; system on chip; time-related faults; Circuit faults; Circuit testing; Decoding; Delay; Fault detection; Random access memory; Silicon; Stress; System testing; System-on-a-chip; PPM reduction.; dynamic faults; memory testing; static faults;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2007. ETS '07. 12th IEEE European

Conference_Location

Freiburg

Print_ISBN

0-7695-2827-9

Type

conf

DOI

10.1109/ETS.2007.33

Filename

4221578