Full-custom all-digital phase locked loop for clock generation

Author

Mu-lee Huang ; Chung-Chih Hung

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

4

Abstract

A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter. With this method, an all-digital PLL can be designed without synthesis procedures. The Digitally-Controlled Oscillator is designed by ring architecture with periodic variation linear. The dynamic range of the TDC is 7.7 ns and the finest resolution of the TDC is only 12.7 ps. System locked time is only 1.62 us. The rms jitter and P-P jitter is 4.68 ps and 38.68 ps in the measurement results. And the power dissipation is only 7.55 mW.

Keywords

clocks; digital control; digital filters; digital phase locked loops; jitter; rings (structures); time-digital conversion; 3-step symmetric time-digital converters; ADPLL; P-P jitter; TDC; ULCD logic; all-digital PLL; clock generation; digitally-controlled oscillator; full-custom all-digital phase locked loop filters; periodic variation linear; power 7.55 mW; power dissipation; ring architecture; rms jitter; synthesis procedures; time 1.62 mus; upper-and-lower-boundaries-cut-off-determination logic; Clocks; Digital filters; Dynamic range; Jitter; Oscillators; Phase locked loops; Timing; All-digital PLL; Digital Loop Filter; Time-to-Digital Converter;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2015.7114567

Filename

7114567