Title :
A 750 Mb/s 0.6 /spl mu/m CMOS two-phase input port using self-tested self-synchronization
Author :
Fenghao Mu ; Svensson, Christer
Author_Institution :
IFM, Linkoping Univ., Sweden
Abstract :
As clock frequency on silicon chips increases continuously, clock phase becomes difficult to control or predict. A method of self-tested self-synchronization, STSS-2, is implemented by a two-phase input port for parallel/series data transfer between modules. In 0.6 /spl mu/m CMOS, a data rate of 750 Mb/s is reached with 3.6 V power supply. There is no need for a test signal, and synchronization is achieved by using the timing relation between the local clock and incoming data.
Keywords :
CMOS digital integrated circuits; ULSI; clocks; synchronisation; timing; 0.6 micron; 3.6 V; 750 Mbit/s; CMOS; STSS-2; ULSI; clock frequency; clock phase; local clock; parallel/series data transfer; self-tested self-synchronization; timing relation; two-phase input port; Built-in self-test; Clocks; Delay; Energy consumption; Frequency synchronization; Jitter; Metastasis; Robustness; Testing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759181
