Low-skew clock generator with dynamic impedance and delay matching

High-speed digital systems on printed circuit boards require low-skew system clock distribution. Previous approaches track fabrication variations in the PC board, but use two traces for each clock to measure round trip delay, or do not dynamically track, both impedance and delay. This clock chip uses both an impedance locked loop (ILL) and a delay locked loop (DLL) for each clock that is generated. Time domain reflectometry dynamically tracks the impedance and delay of the clock wire. Dynamic tracking maintains clock quality in the presence of process and environmental variations such as V/sub dd/ and temperature.