DocumentCode
2728762
Title
Comparison of advanced PoP package configurations
Author
Eslampour, Hamid ; Lee, SeongMin ; Park, SeongWon ; Lee, TaeKeun ; Yoon, InSang ; Kim, YoungChul
Author_Institution
STATS ChipPAC Inc., Fremont, CA, USA
fYear
2010
fDate
1-4 June 2010
Firstpage
1946
Lastpage
1950
Abstract
The continued demand for higher level of integration has led to the industry´s adoption of 3D packaging technologies and, in particular, the Package-On-Package (PoP) configurations. This technology allows for vertical integration of the memory package and the logic package into one stacked package. The top package is primarily a memory module including some combination of Flash and SDRAM, while the bottom package typically contains the logic die, which is a baseband or an application processor of some kind. Top and bottom package are connected via the pads that are located on the top side of the bottom PoP package, and these pads are used to connect the top PoP (memory module) Ball Grid Array (BGA) solder balls to the bottom PoP package. This paper details the various PoP package types including bare-die PoP, Embedded Solder On Pad (eSOP) PoP, and Laser-Via PoP that have proliferated to meet the increasing market demand. Also, the various package types are compared to each other in terms of their feasibility for adoption in the next generation PoP with tighter pitch and lower package profile.
Keywords
Baseband; Bonding; Contamination; Lead; Logic; Packaging; Resins; SDRAM; Stacking; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location
Las Vegas, NV, USA
ISSN
0569-5503
Print_ISBN
978-1-4244-6410-4
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2010.5490687
Filename
5490687
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