• DocumentCode
    2728782
  • Title

    A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

  • Author

    Shimizu, Hiroshi ; Ijitsu, K. ; Akiyoshi, Hirofumi ; Aoyama, Konosuke ; Takatsuka, Hiroki ; Watanabe, K. ; Nanjo, R. ; Takao, Y.

  • Author_Institution
    Adv. CMOS Technol. Dept., Fujitsu Co., Kawasaki, Japan
  • fYear
    1999
  • fDate
    17-17 Feb. 1999
  • Firstpage
    190
  • Lastpage
    191
  • Abstract
    This 1.4 ns 700 MHz 4 kword/spl times/72 b embedded SRAM macro is intended for applications such as cache memory for system LSIs. The macro employs an easily expandable architecture. An 8 kword/spl times/72 b macro can be realized without loss of speed using two 4 kword/spl times/72 b macros.
  • Keywords
    SRAM chips; cache storage; embedded systems; large scale integration; memory architecture; 1.4 ns; 700 MHz; 72 bit; SRAM macro; cache memory; circuit speed; embedded SRAM; expandable architecture; system LSIs; CMOS technology; Clocks; Decoding; Latches; Power dissipation; Pulse amplifiers; Pulse circuits; Pulsed power supplies; Random access memory; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-5126-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.1999.759188
  • Filename
    759188
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2728782