A 500 MHz pipelined burst SRAM with improved SER immunity

Author

Wada, T. ; Ohbayashi, S. ; Sato, H. ; Kozaru, K. ; Okamoto, Y. ; Higashide, Y. ; Shimizu, Tsuyoshi ; Maki, Y. ; Morimoto, R. ; Otoi, H. ; Koga, T. ; Honda, H. ; Taniguchi, Masaaki ; Arita, Yoshihiko ; Shiomi, T.

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

196

Lastpage

197

Abstract

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2 W. This SRAM has to be housed in low-thermal-resistance package such as the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell node capacitance is reduced with reduction of memory cell size. At high altitude (air flight level of 30000 ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type of soft error is significant for mobile applications. The 64k x 36 synchronous pipelined burst SRAM (PBSRAM) described has lower power and improved SER immunity.

Keywords

SRAM chips; cache storage; cellular arrays; cosmic ray interactions; pipeline processing; portable computers; 500 MHz; PBSRAM; SER immunity; TQFP package; cosmic-ray-induced single soft errors; level-2 cache memory; memory cell node capacitance; memory cell size; mobile computer performance; pipelined burst SRAM; power dissipation; CMOS technology; Capacitors; Clocks; Degradation; Latches; MOS devices; Random access memory; Resistors; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759191

Filename

759191