Title :
A 940 MHz data rate 8 Mb CMOS SRAM
Author :
Braceras, G. ; Roberts, A. ; Conner, J. ; Wistort, R. ; Frederick, T. ; Robillard, M. ; Hall, S. ; Burns, S. ; Graf, M.
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
An 8 Mb CMOS SRAM cycles at 470 MHz and provides a data rate of 940 MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4 ns access time. The HSTL I/O performance is enhanced by using flip-chip C4 packaging and by decoupling the I/O supply on-chip. The 8 Mb SRAM has an architecture to allow both /spl times/18 and /spl times/36 organizations, as well as a 4 Mb cut-down.
Keywords :
CMOS memory circuits; SRAM chips; flip-chip devices; integrated circuit packaging; memory architecture; 3.4 ns; 8 Mbit; 940 MHz; CMOS; HSTL I/O performance; I/O supply; SRAM; access time; decoupling; double-data rate mode; flip-chip C4 packaging; memory architecture; Buffer storage; CMOS technology; Circuits; Delay; Latches; Microelectronics; Packaging; Pulse amplifiers; Random access memory; Signal restoration;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759192
