Title :
A Digital Time Delay Measurement Technique and Phase-Locked Loop Requirements in a Standard CMOS Process
Author :
Wey, Todd ; Young, Brian
Author_Institution :
Electr. & Comput. Eng. Dept., Lafayette Coll., Easton, PA
Abstract :
A digital architecture is proposed for measuring time delay increments much smaller than the clock period of a practical operating speed in a standard CMOS process. The technique employs correlated double sampling (CDS), a time-interleaved finite impulse response (FIR) averaging and infinite impulse response (IIR) noise filtering. A system with 200ns peak to peak delay deviation and 10-bit resolution requirement is presented in a 0.5mum CMOS process with an area estimate of 3.5 mm2 and power estimate of 60 mW
Keywords :
CMOS digital integrated circuits; FIR filters; IIR filters; delays; filtering theory; phase locked loops; signal sampling; 0.5 micron; 10 bit; 200 ns; 60 mW; CDS; CMOS process; FIR averaging; IIR noise filtering; correlated double sampling; digital architecture; digital time delay measurement technique; infinite impulse response noise filtering; phase-locked loop requirements in a standard; time-interleaved finite impulse response averaging; CMOS process; Delay effects; Delay estimation; Finite impulse response filter; IIR filters; Measurement standards; Measurement techniques; Phase locked loops; Time measurement; Velocity measurement;
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
DOI :
10.1109/NEWCAS.2006.250964
