VLSI array processor implementation of quasi-block state-space IIR digital filters

Author

Abdel-Raheem, E. ; Tawfik, A.

Author_Institution

Dept. of Electron. & Comm. Eng., Ain Shams Univ., Cairo, Egypt

fYear

1998

fDate

24-26 Feb 1998

Abstract

A new array processor implementation of IIR digital filters is proposed with a high input sampling rate which is not limited by the speed of the processor elements involved. The proposed implementation is based on the quasi-block state-space description of IIR digital filters corresponding to the case of parallel combination of second-order sections. Performance comparison (in terms of hardware complexity and speed) of the proposed implementation with another existing implementation is also presented

Keywords

IIR filters; VLSI; circuit complexity; parallel architectures; signal sampling; VLSI array processor implementation; hardware complexity; input sampling rate; parallel combination; quasi-block state-space IIR digital filters; second-order sections; Availability; Digital filters; Equations; Hardware; IIR filters; Pipeline processing; Sampling methods; State-space methods; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 1998. NRSC '98. Proceedings of the Fifteenth National

Conference_Location

Cairo

Print_ISBN

0-7803-5121-5

Type

conf

DOI

10.1109/NRSC.1998.711464

Filename

711464

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2728959