Impact of Random Bit Values on NBTI Lifetime of an SRAM Cell

Companies estimate the NBTI lifetime of SRAM memories usually by extrapolation of the DC degradation. This method underestimates the lifetime of the memory cell since the bit change in the cell over time is neglected. In this work we have analyzed the impact of storing random bit values in a 6T-SRAM memory cell by using probabilities of storing a one bit between the boundaries of 100% (fully unsymmetric stress) and 50% (symmetric stress). It turned out that the SRAM lifetime for using an unsymmetry of 90% in the stress-split between T2 and T4 is 1.14 times longer than the DC lifetime. We have also demonstrated that the NBTI degradation of the cell converges to the DC degradation for highly unsymmetric stress levels with a probability of over 90% for a one bit. It turned out that the calibrated reaction-diffusion model is useful to study the NBTI response not only for driving the gate with periodic rectangular signals but also for storing random bit sequences in an SRAM cell