Title :
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
Author :
Assaad, Maher ; Cumming, David R S
Author_Institution :
Univ. of Glasgow, Glasgow
Abstract :
The results of design and simulation of a novel architecture for a 10 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the serializer/deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 mum CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.
Keywords :
CMOS integrated circuits; clocks; electronic engineering computing; hardware description languages; integrated circuit design; logic design; synchronisation; system-on-chip; 10-Gb/s PLL-based deserializer; CMOS IC design; SOC; Verilog-A modelling; clock-and-data recovery circuit; inter-chip communication; referenceless quarter-rate design; serializer/deserializer device; CMOS integrated circuits; CMOS logic circuits; Circuit simulation; Clocks; Communication networks; Hardware design languages; Integrated circuit modeling; Phase detection; Phase frequency detector; Semiconductor device modeling;
Conference_Titel :
System-on-Chip, 2007 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-1368-3
Electronic_ISBN :
07EX1846C
DOI :
10.1109/ISSOC.2007.4427420
