DocumentCode :
2729304
Title :
A 52 Mb/s universal DSL transceiver IC
Author :
Joshi, R.B. ; Yang, Ping ; Huan-Chang Liu ; Kindsfater, K. ; Cameron, Katherine ; Gee, D. ; Hung Vu ; Gorman, G. ; Shauhyuam Tsai ; Ada Hung ; Khan, Raees ; Lee, Onyou ; Tollefsrud, S. ; Berg, E.C. ; Jind-Yeh Lee ; Kwan, T. ; Chi-Hung Lin ; Buchwald, A. ;
Author_Institution :
Broadcom Corp., Irvine, CA, USA
fYear :
1999
fDate :
17-17 Feb. 1999
Firstpage :
250
Lastpage :
251
Abstract :
A twisted-pair quadrature amplitude modulation (QAM) transceiver IC accommodates data rates from 0 to 52 Mb/s. The QAM transceiver is a monolithic mixed signal device implemented in 0.35 /spl mu/m four-level metal single-poly CMOS. The transceiver supports 4-, 16-, 32-, 64-, 128-, and 256-QAM modulation formats and operates at symbol rates as high as 13 MBaud. The transceiver chip contains a fully-integrated transmitter, including ATM UTOPIA or synchronous input interface, packet-formatting logic, Reed-Solomon forward error correction (FEC) encoding, a rate-adaptive QAM modulator and a 10 b D/A converter. The receiver portion of the transceiver chip consists of a high-precision 10 b A/D converter, a programmable rate QAM demodulator, all-digital clock and carrier recovery loops, powerful adaptive filters to provide rejection of narrowband interferers and the equalization of severe channel distortions, FEC decoding, ATM UTOPIA or synchronous output interface and an analog phase-lock loop for internal clock generation from a single crystal reference. The QAM transceiver may be used in applications such as asymmetric digital subscriber line (ADSL) and very high-speed digital subscriber line (VDSL) services.
Keywords :
CMOS integrated circuits; Reed-Solomon codes; adaptive filters; asynchronous transfer mode; digital subscriber lines; error correction codes; mixed analogue-digital integrated circuits; quadrature amplitude modulation; transceivers; twisted pair cables; 0.35 micron; 10 bit; 52 Mbit/s; ATM UTOPIA; FEC decoding; Reed-Solomon forward error correction encoding; adaptive filters; all-digital clock; analog phase-lock loop; asymmetric digital subscriber line; carrier recovery loops; data rates; four-level metal single-poly CMOS; fully-integrated transmitter; internal clock generation; mixed signal device; narrowband interferers; packet-formatting logic; programmable rate QAM demodulator; quadrature amplitude modulation; rate-adaptive QAM modulator; severe channel distortions; symbol rates; synchronous input interface; twisted-pair; universal DSL transceiver IC; very high-speed digital subscriber line; CMOS logic circuits; Clocks; DSL; Demodulation; Forward error correction; Logic devices; Quadrature amplitude modulation; Reed-Solomon codes; Transceivers; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
0-7803-5126-6
Type :
conf
DOI :
10.1109/ISSCC.1999.759223
Filename :
759223
Link To Document :
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