Superior-Order Curvature-Corrected Logarithmic CMOS Nanostructure

A new high precision superior-order curvature-corrected integrated nanostructure will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary to absolute temperature) voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the integrated nanostructure, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (Proportional To Absolute Temperature) and PTAT². The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 9.4 ppm/K for an extended input range 173 K<T<423 K and for a supply voltage of 2.5 V and a current consumption of about 1 uA.