Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture

Author

Ito, Kiyoto ; Shibata, Tadashi

Author_Institution

Univ. of Tokyo, Tokyo

fYear

2007

fDate

20-21 Nov. 2007

Firstpage

1

Lastpage

4

Abstract

A mixed-signal focal-plane image processor for realtime spatiotemporal convolution has been developed based on the time-domain computation technique. Pixel information is represented as a pulse width, and all computations are carried out using simple digital logic gates and a binary counter equipped in each pixel processing element. As a result, both the compactness of analog and programmability of digital have been achieved. The concept was verified by a prototype chip fabricated in a 0.18-mum CMOS technology, demonstrating over 78,000 convolutions/s with 1.0V supply.

Keywords

CMOS logic circuits; convolution; counting circuits; image resolution; logic gates; spatiotemporal phenomena; CMOS technology; binary counter; digital logic gates; mixed-signal focal-plane image processor; pixel processing element; prototype chip; realtime spatiotemporal convolution; time-domain computation architecture; CMOS logic circuits; CMOS technology; Computer architecture; Convolution; Counting circuits; Logic gates; Prototypes; Space vector pulse width modulation; Spatiotemporal phenomena; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2007 International Symposium on

Conference_Location

Tampere

ISSN

07EX1846C

Print_ISBN

978-1-4244-1368-3

Electronic_ISBN

07EX1846C

Type

conf

DOI

10.1109/ISSOC.2007.4427428

Filename

4427428