DocumentCode
2729446
Title
PC-TRIO: An indexed TCAM architecture for packet classifiers
Author
Banerjee-Mishra, Tania ; Sahni, Sartaj ; Seetharaman, Gunasekaran
Author_Institution
Univ. of Florida, Gainesville, FL, USA
fYear
2012
fDate
1-4 July 2012
Abstract
We propose an indexed TCAM architecture, PC-TRIO, for packet classifiers. PC-TRIO uses wide SRAMs and index TCAMs. On our classifier datasets, PC-TRIO on an average reduced TCAM power by 96% and lookup time by 98%, compared to PC-DUOS+ [23] that does not use indexing or wide SRAMs. We extend PC-DUOS+ by augmenting it with wide SRAMs and index TCAMs using the same methodology as used in PC-TRIO, to obtain PC-DUOS+W. On ACL datasets, PC-DUOS+W reduced TCAM power by 86% and lookup time by 98%, compared to PC-DUOS+.
Keywords
Internet; SRAM chips; content-addressable storage; telecommunication network routing; PC-DUOS+W; PC-TRIO; SRAM; indexed TCAM architecture; lookup time; packet classifiers; Computer architecture; Encoding; Indexing; Power demand; Protocols; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications (ISCC), 2012 IEEE Symposium on
Conference_Location
Cappadocia
ISSN
1530-1346
Print_ISBN
978-1-4673-2712-1
Electronic_ISBN
1530-1346
Type
conf
DOI
10.1109/ISCC.2012.6249316
Filename
6249316
Link To Document