Title :
A 2.5 GFLOPS 6.5 million polygons per second 4-way VLIW geometry processor with SIMD instructions and a software bypass mechanism
Author :
Higaki, N. ; Kubosawa, H. ; Ando, Shin ; Takahashi, Hiroki ; Asada, Yuma ; Anbutsu, H. ; Sato, Takao ; Sakate, M. ; Suga, A. ; Kimura, Mizue ; Miyake, Hirokazu ; Okano, Hiroshi ; Asato, A. ; Kimura, Yuichi ; Nakayama, Hiroki ; Kimoto, M. ; Hirochi, K. ; S
Author_Institution :
Fujitsu Labs. Ltd., Tokyo, Japan
Abstract :
A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.
Keywords :
CMOS digital integrated circuits; circuit tuning; clocks; instruction sets; integrated circuit design; microprocessor chips; parallel architectures; 0.21 micron; 2.5 GFLOPS; 2.5 V; 312 MHz; 3D geometry processor; PCI/AGP bus bridge; SIMD instructions; automatic clock delay tuning; branch condition generator; condition-code registers; design rules; four-way VLIW geometry processor; software bypass mechanism; three-layer-metal CMOS process; Costs; Delay; Geometry; Graphics; Hardware; Logic; Personal communication networks; Reduced instruction set computing; Registers; VLIW;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759233
