A 32 b 64-matrix parallel CMOS processor

The /spl beta/ chip is a 32 b floating-point processor with 64-matrix parallel computing units using CMOS 0.35 /spl mu/m technology. The /spl beta/ chip is intended for use as a DSP coprocessor in a PC environment or in other computational-intensive applications. Such applications include digital filter (FIR, IIR), matrix multiplication, nonlinear polynomial calculations, DCT, DFT, video compression, and 3D graphics. In each computing unit (CU), all calculations are in the logarithm domain except some special instructions. The absolute error using the logarithm operation is less than 1 LSB in IEEE 32 b floating-point format. There is a 128/spl times/32 b memory (cache) in each CU. The total memory (cache) is 32 kB on the chip. There are three I/O buses on the chip; input data bus, output data bus and host control bus. The average sustained performance can reach 10 GFLOPS.