DocumentCode
2729546
Title
A fully-parallel 1 Mb CAM LSI for real-time pixel-parallel image processing
Author
Ikenaga, Takeshi ; Ogura, Tsuneo
Author_Institution
NTT Integrated Inf. & Energy Syst. Labs, Japan
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
264
Lastpage
265
Abstract
For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM) that performs parallel data processing with words as the basic unit is a promising component of a compact highly parallel image processing system because of its suitability for LSI implementation. Conventional CAM LSIs, however, do not have efficient transfer of data between words. This limits image-processing applications. Moreover, they do not have enough capacity. More chips are required for pixel-order parallelism. This 1 Mb CAM LSI has dedicated functions for image processing, including data transfer. It performs two-dimensional pixel-parallel or cellular automation processing. Since it has 16 k words or processing elements (PEs) which process 128/spl times/128 pixels, a board-sized fully pixel-parallel image-processing system can be implemented using several chips.
Keywords
content-addressable storage; digital signal processing chips; image processing equipment; large scale integration; parallel architectures; real-time systems; 1 Mbit; 128 pixel; 16384 pixel; LSI implementation; cellular automation processing; content addressable memory; data transfer; fully-parallel CAM LSI; processing elements; real-time pixel-parallel image processing; two-dimensional pixel-parallel processing; CADCAM; Circuits; Clocks; Computer aided manufacturing; Delay; Image processing; Large scale integration; Pixel; Registers; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759238
Filename
759238
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