Flip-flop selection technique for power-delay trade-off [video codec]

Author

Hamada, Mohamed ; Terazawa, T. ; Higashi, T. ; Kitabayashi, S. ; Mita, Seiichi ; Watanabe, Yoshihiro ; Ashino, M. ; Hara, Hideki ; Kuroda, Tadahiro

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

270

Lastpage

271

Abstract

Circuit and design techniques trade off power, delay, and area of a chip by blending different types of flip-flops with different merits: F/F blending. Three types of discrete cosine transform (DCT) blocks for MPEG-4 video codec, a conventional design (Conv-DCT), a low-power design (LP-DCT), and a high-speed design (HS-DCT), are fabricated in a 0.3 /spl mu/m CMOS technology. LP-DCT consumes 24%-51% less power without speed degradation, and HS-DCT operates 25% faster than Conv-DCT.

Keywords

CMOS digital integrated circuits; delays; discrete cosine transforms; flip-flops; high-speed integrated circuits; low-power electronics; video codecs; 0.3 micron; F/F blending; HS-DCT; LP-DCT; MPEG-4 video codec; discrete cosine transform; flip-flop selection technique; high-speed design; low-power design; power-delay trade-off; speed degradation; Clocks; Costs; Delay; Discrete cosine transforms; Energy consumption; Flip-flops; MPEG 4 Standard; Power dissipation; Solid state circuits; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759241

Filename

759241