A 1.9 V I/O buffer with gate-oxide protection and dynamic bus termination for 400 MHz UltraSparc microprocessor

Transistors fabricated with thin gate-oxides are vulnerable to dielectric damage and reliability problems due to excessive electric field. Recently, the difference between operating voltage and maximum allowed gate-source voltage (Vgs) and gate-drain voltage (Vgd) of MOS transistors has decreased significantly. This presents special challenges for I/O designers, since transistors used in I/O buffers are subjected to higher Vgs/Vgd than those used in the core because of switching noise, signal reflections, and ground bounce. The problem is worse in chip redesign projects due to layout area, supply and methodology constraints. In this application, the microprocessor redesign is targeted to 1.9V technology in 0.21/spl mu/m process which imposes the constraint of 2.2V and 1.9V as the maximum transient and DC limits.