Title :
A 18 /spl mu/A-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode
Author :
Mizuno, Hidenori ; Ishibashi, Koji ; Shimura, Toshihiro ; Hattori, Toshihiro ; Narita, S. ; Shiozawa, Kousuke ; Ikeda, Shoji ; Uchiyama, Kenji
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A 1.8 V 200 MHz low-subthreshold-leakage-current microprocessor is fabricated in a 0.2 /spl mu/m CMOS technology. It uses a switched substrate-impedance scheme to bias substrates while maintaining 200 MHz operating speed. It also offers a battery backup capability in a self substrate-biased data retention mode, in which it consumes only 17.8 /spl mu/A operating off a 1.0 V supply.
Keywords :
CMOS digital integrated circuits; integrated circuit reliability; leakage currents; microprocessor chips; 0.2 micron; 1.8 V; 18 muA; 200 MHz; CMOS technology; battery backup capability; data retention mode; microprocessor; operating speed; self substrate-biased data-retention mode; standby current; subthreshold leakage current; switched substrate-impedance scheme; Batteries; CMOS technology; Impedance; Integrated circuit interconnections; Logic circuits; MOSFETs; Microprocessors; Switches; Variable structure systems; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759250
