Title :
Asynchronous sense differential logic
Author :
Bai-Sun Kong ; Jeong-Don Im ; Youn-Cheul Kim ; Seong-Jin Jang ; Young-HyunJun
Author_Institution :
LG Semicon, Seoul, South Korea
Abstract :
Charge-recycling differential logic (CRDL) implements energy-efficient operation by recycling already used charge. This technique requires p-channel devices with higher threshold for maximum efficiency. Half-rail differential logic (HRDL) avoids the drawback at the expense of performance. These circuits are prone to pre-evaluation discharge during evaluation when not properly designed. Asynchronous sense differential logic (ASDL) improves energy efficiency with no threshold change or performance degradation.
Keywords :
asynchronous circuits; delays; logic gates; timing; asynchronous sense differential logic; energy efficiency; performance degradation; pre-evaluation discharge; threshold; Acceleration; Degradation; Delay; Inverters; Logic circuits; Logic devices; Signal generators; Timing; Variable speed drives; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759254