DocumentCode
2729805
Title
Simplified check node processing in nonbinary LDPC decoders
Author
Boutillon, E. ; Conde-Canencia, L.
Author_Institution
Lab.-STICC, Univ. Europeenne de Bretagne, Lorient, France
fYear
2010
fDate
6-10 Sept. 2010
Firstpage
201
Lastpage
205
Abstract
This paper deals with low-complexity algorithms for the check node processing in nonbinary LDPC decoders. After a review of the state-of-the-art, we focus on an original solution to significantly reduce the order of complexity of the Extended Min-Sum decoder at the elementary check node level. The main originality of the so-called Bubble Check algorithm is the two-dimensional strategy for the check node processing, which leads to a reduction of the number of comparisons. The simulation results obtained for the Bubble Check show that this complexity reduction does not introduce any performance loss and that it is even possible to further reduce the number of comparisons. This motivated the search of a simplified architecture and led to the L-Bubble Check, which is the main contribution of the paper. The implementation of a forward/backward check node as a systolic architecture of L-Bubble elementary checks is also described. Finally, some FPGA synthesis results of a whole GF(64)-LDPC decoder implementation are presented.
Keywords
binary codes; parity check codes; bubble check algorithm; check node processing; forward-backward check node; min-sum decoder; nonbinary LDPC decoder; Frequency modulation; Registers; FPGA synthesis; Nonbinary low-density parity-check decoders; check node processing; decoder implementation; simplified architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Turbo Codes and Iterative Information Processing (ISTC), 2010 6th International Symposium on
Conference_Location
Brest
Print_ISBN
978-1-4244-6744-0
Electronic_ISBN
978-1-4244-6745-7
Type
conf
DOI
10.1109/ISTC.2010.5613839
Filename
5613839
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