A 75 mW 10 b 20 MSample/s CMOS subranging ADC with 59 dB SNDR

In a two-step CMOS subranging ADC (CSA), a coarse comparator bank determines which subset of fine reference taps from a resistor ladder should be passed (without amplification or subtraction from the ADC input) to a fine comparator bank by an analog multiplexer (AMUX). This CSA provides advantages over previously-reported variations of this architecture. These advantages include absolute value signal processing, an extended settling period for the fine references, a fully differential topology, and a front-end sample-and-hold amplifier (SHA). As a result of these features, this ADC achieves 9.5 ENOB Nyquist performance at 75 mW and two-clock-cycle conversion latency.