An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter

Author

Joonbae Park ; Wonchan Kim

Author_Institution

Seoul Nat. Univ., South Korea

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

350

Lastpage

351

Abstract

This clock recovery circuit has auto-ranging. A time-to-digital converter (TDC) rather than a frequency detector is employed for accurate information about the cycle time of the incoming data. This auto-ranging circuit, which operates in the time domain, eliminates the inherent problems of harmonic locking found in conventional circuits. This circuit is configured as a triple-loop structure, which consists of a center frequency-tuning loop, a frequency detecting loop, and a phase detecting loop.

Keywords

analogue-digital conversion; circuit tuning; phase detectors; synchronisation; 50 to 210 Mbit/s; auto-ranging circuit; center frequency-tuning loop; clock recovery circuit; cycle time; frequency detecting loop; harmonic locking; phase detecting loop; time-to-digital converter; triple-loop structure; Circuits; Clocks; Frequency conversion; Frequency locked loops; Phase detection; Phase frequency detector; Pulse measurements; Registers; Space vector pulse width modulation; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759288

Filename

759288