Chip package interaction (CPI) reliability of low-k/ULK interconnect with lead free technology

The introduction of low-k/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling-down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties of interlayer dielectric material (ILD). Implementation of crackstop and improve low-k/ULK mechanical properties are very effective to protect ILD crack propagation and delamination. Finite element analysis (FEA) simulation and Shadow Moire measurements showed higher die stress with lead free bumps. Reflow simulated Shadow Moire measurements show a large warpage change from 150°C to 25°C, good control of the ramp rate is needed. Die warpage releases 50% after 30 days.