Title :
Settling-time-oriented design procedure for two-stage amplifiers with current-buffer Miller compensation
Author :
Pugliese, A. ; Amoroso, F.A. ; Cappuccino, G. ; Cocorullo, G.
Author_Institution :
Dept. of Electron., Univ. of Calabria, Rende
Abstract :
A novel design procedure for two-stage operational amplifiers (op-amps) with current-buffer Miller compensation (CBMC) is proposed. The method is based on equations which relate both bias current and aspect ratio of transistors to the main amplifier parameters. The important innovation of the procedure is the definition of a systematic strategy to achieve the desired settling time by performing the op-amp dynamic behaviour optimization, which is badly needed in high-performance discrete-time applications. To prove the effectiveness of the proposed approach, a design example of a CBMC op-amp in 0.35 mum CMOS technology is presented.
Keywords :
CMOS analogue integrated circuits; compensation; integrated circuit design; operational amplifiers; CMOS technology; amplifier parameter; bias current; current-buffer Miller compensation; discrete-time applications; settling-time-oriented design procedure; size 0.35 mum; transistor aspect ratio; two-stage amplifiers; two-stage operational amplifiers; CMOS technology; Computer science; Design methodology; Equations; Frequency; Network topology; Operational amplifiers; Performance gain; Stability; Technological innovation;
Conference_Titel :
Circuits and Systems for Communications, 2008. ECCSC 2008. 4th European Conference on
Conference_Location :
Bucharest
Print_ISBN :
978-1-4244-2419-1
Electronic_ISBN :
978-1-4244-2420-7
DOI :
10.1109/ECCSC.2008.4611658
