DocumentCode
2730359
Title
The impact of technology evolution and scaling on electrostatic discharge (ESD) protection in high-pin count high-performance microprocessors
Author
Voldman, S.H.
Author_Institution
IBM Microelectron., Essex Junction, VT, USA
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
366
Lastpage
367
Abstract
The technology evolution of MOSFET junctions, salicide technology, well, epitaxy, isolation, copper (Cu) interconnects, low-k interlevel dielectrics (ILD), and transition from bulk-CMOS to silicon-on-insulator (SOI) and their influence on ESD robustness in high-performance microprocessors are discussed here.
Keywords
electrostatic discharge; integrated circuit interconnections; isolation technology; microprocessor chips; silicon-on-insulator; ESD robustness; IC interconnects; MOSFET junctions; SOI; electrostatic discharge protection; epitaxy; high-performance microprocessors; interlevel dielectrics; isolation; salicide technology; scaling; technology evolution; Biological system modeling; Copper; Diodes; Electrostatic discharge; Integrated circuit interconnections; Isolation technology; MOSFET circuits; Protection; Robustness; Silicon on insulator technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759298
Filename
759298
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