A 13 mW 500 kHz data acquisition IC with 4.5 digit DC and 0.02% accurate true-RMS extraction

This mixed-signal 0.5 /spl mu/m CMOS data-acquisition IC uses a second-order 5b /spl Sigma//spl Delta/ modulator for A/D conversion of a 500 kHz input bandwidth. Signal properties like DC, true-RMS (TRMS), peak and frequency are extracted in the digital domain. The article shows a traditional data-acquisition block diagram. Analog filtering extracts DC and RMS value, peak min/max and frequency. A high-resolution A/D converter (100 dB for 4.5 digit resolution) digitizes the resulting low-frequency signal (typically 2 Hz). If waveform display of the input signal is desired, a separate 6-8b high-speed A/D converter is required. One of the problems with such an acquisition system is the analog RMS converter, which requires bulky external filter capacitors, is slow responding (especially for low-level inputs), has limited dynamic range, and has limited bandwidth when operated at low power.