• DocumentCode
    2730701
  • Title

    A 1.6 GB/s DRAM with flexible mapping redundancy technique and additional refresh scheme

  • Author

    Takase, S. ; Kushiyama, N.

  • Author_Institution
    Toshiba Corp., Yokohama, Japan
  • fYear
    1999
  • fDate
    17-17 Feb. 1999
  • Firstpage
    410
  • Lastpage
    411
  • Abstract
    This DRAM features (1) interleaved operation of 16 dependent banks with 1.6 GB/s data rate, (2) flexible mapping redundancy which suits multi-bank memory, and (3) additional-refresh that realizes a low data retention power DRAM.
  • Keywords
    DRAM chips; interleaved storage; redundancy; 1.6 GB/s; DRAM; data retention; flexible mapping redundancy technique; interleaved operation; multi-bank memory; refresh scheme; Bandwidth; Circuits; Decoding; Distribution functions; Fuses; Latches; Logic; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-5126-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.1999.759326
  • Filename
    759326
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2730701