A 2.5 V 333 Mb/s/pin 1 Gb double data rate SDRAM

While on-chip data flight times approach a few tens of nanoseconds for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input and output timing accuracy within 0.3 ns. Although a high-speed data interface can be achieved using precise clock generators such as delay locked loop (DLL), skews due to a long data access path may cause loss of internal timing margins. Diminished timing margin may be detrimental to wave pipelining for high-bandwidth. This 1 Gb double data rate (DDR) SDRAM featuring ODIC chip with nonODIC package (OCNOP), cycle-time-adaptive wave pipelining (CTAWP), and variable stage analog DLL achieves high performance despite stringent processing variations in 0.14 /spl mu/m design rules.