Application of the latency insertion method (LIM) to the modeling of CDM ESD events

In this paper, the application of the latency insertion method (LIM) to the analysis of charged device model (CDM) electrostatic discharge (ESD) events in integrated circuits (ICs) is discussed. LIM is proposed as an alternative to existing techniques commonly used for chip-level circuit simulation of CDM ESD. Such simulators, based on the modified nodal analysis (MNA) method, can underperform in cases that require very large model sizes. LIM was developed specifically for the analysis of fast transient phenomena in very large networks and is more robust and less resource-hungry than conventional methods.