A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

Author

Allen, D.H. ; Aipperspach, A.G. ; Cox, D.T. ; Phan, N.V. ; Storino, S.N.

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

438

Lastpage

439

Abstract

A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a silicon-on-insulator (SOI) version of the same technology. Some architectural changes improve CPI, including doubling the L1 instruction and data caches to 128 kB and adding a 256 kB L2 directory. The total transistor count increased from 12 M to 34 M.

Keywords

CMOS digital integrated circuits; cache storage; copper; integrated circuit interconnections; microprocessor chips; reduced instruction set computing; silicon-on-insulator; 0.2 micron; 1.8 V; 128 kB; 256 kB; 550 MHz; 64 bit; CMOS technology; Cu interconnects; L2 directory; PowerPC microprocessor; RISC microprocessor; SOI version; Si; data caches; instruction caches; multi-threshold transistors; CMOS technology; Circuit noise; Copper; Delay; Frequency; Integrated circuit interconnections; Microprocessors; Silicon on insulator technology; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759345

Filename

759345