Title :
Time-domain simulation of system interconnect using convolution and Newton-Raphson iteration methods
Author :
Cocchini, Matteo ; Becker, Wiren Dale ; Katopis, George ; Pytel, Steven Gary, Jr.
Author_Institution :
IBM STG Group, Poughkeepsie, NY, USA
Abstract :
In today´s world electronic system interconnections, commonly called channels, are routed over packages and printed circuit boards and are characterized by measuring eyes and calculating the bit error rate (BER). Many factors such as jitter, inter-symbol interference, simultaneous switching noise and crosstalk impact the BER of an interconnection. In the design phase, it is common practice to use circuit simulation to guarantee an acceptable BER level. This is done by acquiring the voltage waveform at the input of the receiver circuit in a robust statistical manner using time domain simulations. The possible time-domain simulation techniques can be classified in two ways: a transient solver (e.g., ASTAP, Spice) which uses non-linear Newton-Raphson iteration methods, and another second technique based on linear convolution and which has gained wide acceptance more recently due to the large number of bits that can be simulated. In this work, the two methods are applied for the timedomain analysis of a real interconnection system represented by the concatenation of 52 mixed 2-D and 3-D models. The 3D models are needed to describe the high-order modes in proximity of package discontinuities, such as via transitions and connectors. The ports of these models range in number from 18 to 36 depending on the number of aggressors that can create significant crosstalk. In this work the required rules of thumb derived from a sampling criterion will be described, so that the correct sampling frequency of the S-parameter models can be determined and robust simulation results for such a large cascaded netlist can be achieved. The overall interconnection model includes behavioral models for the driver and receiver circuits that employ equalization. Behavioral models give a needed simplification because the complexity of the original transistor-level I/O circuits leads to unacceptable long simulation times. We will use the analysis of the described real interconnection system to com- - pare the two transient simulation approaches and quantify their expected accuracy. Furthermore, the limitations of the existing simulation methods in handling complex interconnections will be discussed, with particular emphasis on the checking and enforcement of causality and passivity for these models.
Keywords :
Bit error rate; Circuit simulation; Convolution; Crosstalk; Electronics packaging; Eyes; Integrated circuit interconnections; Printed circuits; Sampling methods; Time domain analysis;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
978-1-4244-6410-4
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2010.5490811