Title :
Optimization and Elimination of Parasitic Latchup in Advanced Smart Power Technologies
Author :
Zhu, R. ; Khemka, V. ; Bose, A. ; Roggenbauer, T.
Author_Institution :
Freescale Semicond. Inc., Tempe, AZ
Abstract :
This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart power technology. The impact of logic ground isolation from the substrate and the presence of P+ and N+ buried layers below the logic wells is quantified
Keywords :
CMOS integrated circuits; buried layers; integrated circuit reliability; isolation technology; power integrated circuits; 0.25 micron; CMOS latchup immunity; buried layers; logic ground isolation; logic wells; smart power technology; CMOS logic circuits; CMOS process; CMOS technology; Implants; Isolation technology; Logic devices; Robustness; Silicon; Substrates; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9498-4
Electronic_ISBN :
0-7803-9499-2
DOI :
10.1109/RELPHY.2006.251209
